In general, in order to manufacture semiconductor devices, a semiconductor wafer is repeatedly subjected to various treatments such as a film forming process and a pattern etching process to form desired devices. With increased requirements for highly integrated and miniaturized semiconductor devices, a line width and/or a hole diameter of the device is currently being reduced. Along with reduction in various dimensions of the device, a lower electric resistance is required. In order to meet the requirement, copper with economic merit and low electric resistance tends to be used as a wiring material and/or a material buried in recess such as trenches, holes, and the like (see, e.g., Japanese Laid-open Publication No. 2004-107747 and corresponding U.S. Patent Application Publication No. 2006-037858). When copper is used as the wiring material and/or the buried material, a tantalum metal (Ta) or a tantalum nitride (TaN) film is generally used as a barrier layer in consideration of diffusion barrier properties of copper to a layer thereunder.
In order to bury copper in a recess, first of all, a thin seeding film of a pattern film is formed on the entire surface of a wafer including an entire wall surface of the recess in a plasma sputtering apparatus. Then, copper plating is performed on the entire surface of the wafer to completely bury copper in the recess. Afterwards, a residual copper thin film remaining on the wafer surface is polished and removed by chemical mechanical polishing (CMP).
Referring to FIGS. 12A to 12C, burying of copper will be described in detail below. FIGS. 12A to 12C illustrate a conventional burying process for a recess of a semiconductor device. An insulating layer 1, e.g., an interlayer insulating film, formed on a semiconductor wafer W has a recess 2 corresponding to a via hole, through hole, groove (trench or dual damascene structure) or the like on the surface thereof. A lower wiring layer 3 made of, e.g., copper is exposed on the bottom of the recess 2.
Specifically, the recess 2 includes a long and narrow groove (trench) 2A and a hole 2B formed at a part of the bottom of the groove 2A. The hole 2B may be a contact hole or a through hole. The wiring layer 3 is exposed on the bottom of the hole 2B (FIG. 12A shows the wiring layer 3 covered with a barrier layer 4). The electrical connection with a lower wiring layer and/or another device such as a transistor is made through the wiring layer 3. Illustration of the lower wiring layer and/or the device such as a transistor is omitted from the drawing.
The insulating layer 1 may be formed of, e.g., an SiO2 film. A width or an inner diameter of the recess 2 is drastically reduced to about 120 nm and an aspect ratio of the recess 2 may range from about 2 to 4 in response to design rules for miniaturization of devices. Further, illustration of a diffusion barrier film and an etching stopper film will be omitted for simplicity.
A barrier layer 4 with a stack structure of, e.g., a TaN film and a Ta film is pre-formed on a surface of the semiconductor wafer W (including an inner surface of the recess 2) by using the plasma sputtering apparatus (see FIG. 12A). Then, a seeding film 6 of a thin copper film is formed on the entire surface of the semiconductor wafer W (including the inner surface of the recess 2) by using another plasma sputtering apparatus (see FIG. 12B). When the seeding film 6 is formed by the plasma sputtering apparatus, a high frequency bias power is applied to the semiconductor wafer and introduction of copper ions is efficiently performed. Next, copper plating is performed on the surface of the wafer to bury a metal film 8 of a copper film in the recess 2 (see FIG. 12C). Afterwards, undesired portions of the metal film 8, the seeding film 6 and the barrier layer 4 remaining on the surface of the wafer are eliminated by a polishing process such as CMP.
However, a variety of investigations into development of a barrier layer with improved reliability are currently conducted and, in particular, a self-formable barrier layer using a Mn film or a CuMn alloy film instead of Ta and/or TaN films has been receiving attention (see Japanese Laid-open Publication No. 2005-277390 and corresponding U.S. Patent Application Publication No. 2005-218519). The Mn film (or CuMn alloy film) is formed by sputtering. Since the Mn film (or CuMn alloy film) becomes a seeding film, a Cu plated layer may be formed directly on the seeding film. Further, annealing the film after Cu plating induces a self-alignment reaction of the Mn film (or CuMn alloy film) with an SiO2 layer serving as an insulating layer below the Mn film (or CuMn alloy film), thereby forming a barrier film at a boundary between the SiO2 layer and the Mn film (or CuMn alloy film), wherein the barrier film is formed of a MnSixOy film (x, y: random positive) and/or a manganese oxide MnOx (x: random positive). Therefore, the number of manufacturing processes is preferably reduced. The manganese oxide includes oxides of manganese with different atomic valences, e.g., MnO, Mn3O4, Mn2O3, and MnO2, and will be hereinafter referred to as MnOx.
In practical applications, the Mn film (CuMn alloy film) is only formed by sputtering. Since step coverage attained by a sputtering method has restrictions, the sputtering method may hardly conform with film formation in a future device with an extremely fine pattern, e.g., formation of a film in a trench and/or hole of the device wherein a line width and/or a hole diameter of the trench and/or hole is equal to or smaller than 32 nm.
Furthermore, formation of the seeding film 6 (Mn film or CuMn alloy film), Cu plating and/or annealing must employ respective apparatuses suitable for individual processes, that is, a sputtering apparatus, an electroplating apparatus and an annealing apparatus, respectively. Accordingly, an increase in total installation costs (equipment costs) cannot be avoided.
As for formation of a Mn film (CuMn alloy film) by sputtering, a thick film is formed on the bottom of a recess rather than a sidewall thereof. Therefore, even if a sufficiently thin MnSixOy film is generated on the sidewall of the recess after an annealing process, a large amount of Mn or MnOx with higher resistance than copper remains on the bottom of the recess. As a result, the film has a problem of high contact resistance.